Location: Virtual Classroom
Instructor: Joe Winkles
Duration: 8 half-days
Date: 03/16/27 to 03/19/27
and: 03/22/27 to 03/25/27
Time: 1pm-4:30pm US Pacific Time Daily
$2995.00
Price per Learner (volume discounts available for 5 or more learners; contact us for more details)
Overview
MindShare's PCI Express 6.x/7.0 Update course starts with a discussion of what’s new in the 6.x and 7.0 specs and why the introduction of PAM4 signaling caused the need for Flits and forward error correction.
This MindShare course requires prior knowledge of PCIe 5.0. Only the new features of 6.x and 7.0 are covered with a light review of 5.0 features/behaviors that have changed moving into 6.x and 7.0 with Flit Mode.
Course Outline
- Overview of PCIe 6.x/7.0 features
- Refresher of PCIe 5.0 topics
- Bus enumeration
- TLP and DLLP fields
- Flow Control
- AckNak error recovery mechanism
- Ordered Sets
- Equalization mechanism
- 64GT/s and 128GT/s using PAM4 and 1b/1b Encoding at the Physical Layer (PCIe6)
- PAM4
- Precoding, Gray Coding and Forward Error Correction (FEC)
- LTSSM Updates (TS0s, Tx EQ changes, entering Flit Mode, etc.)
- Support of upto 4 Retimers per link
- Flit Mode
- Flit Format
- Error Correction and Flit Retry (Standard vs Selective)
- DLP Bytes in Flit and Flit Types
- Flow Control (Dedicated vs Shared)
- TLP Structure (Header Base, OHC, TLP Trailer, etc.)
- Segments
- L0p
- Unordered IO (UIO)
- Overview of PCIe Management Interface (PCIe-MI)
- Enhanced SFI (eSFI)
- Shadow Functions vs Phantom Functions
- Device 3 Extended Capability Structure
- Shadow Functions Extended Capability Structure
- Power Budgeting new features
Training Materials
- PDF of course slides
- PCIe6 Update eLearning course
- PCIe 6.x/7.0 Update eLearning course (when available in Q3, 2026)
Prerequisites
A good understanding of PCI Epress 5.0 Architecture.