Location: Virtual Classroom
Instructor: Mike Jackson
Duration: 10 half-days
Date: 03/01/27 to 03/05/27
and: 03/08/27 to 03/12/27
Time: 1pm-4:30pm US Pacific Time Daily
$3495.00
Price per Learner (volume discounts available for 5 or more learners; contact us for more details)
Overview
MindShare's PCI Express System Architecture course starts with a high-level view of the technology to provide the big-picture context and then drills down into the details for each topic, providing a thorough understanding of the hardware and software protocols.
The course describes additional features added to the architecture when moving through the PCIe specification revisions from 1.1 all the way to the latest 6.2. There are a large number of features and optional behaviors described in the PCIe spec. MindShare can customize the course to cover the topics that are most important for your group. Use the course outline below as a guide to request topics you want covered or removed. The table below contains a list of suggested course customizations.
Course Outline
Topics Below Are To Be Covered Via MindShare's PCIe Fundamentals eLearning Mandatory Self-Study Prework
- PCI Architecture Background Foundation
- PCI concepts important for understanding PCI Express
- Physical Address Spaces
- Traffic Types (System Memory, PIO and DMA)
- Typical System Transactions (NVMe Example)
- PCI Express Features and Architecture Overview
- Layered Architecture
- ARM example topology
- TLP, DLLP and Ordered Set Packet Format Overview
- Protocol Overview
- Configuration Overview
- Legacy and Enhanced Configuration Access Mechanism (ECAM)
- Type 0 and Type 1 Headers, Capability and Extended Capability Structures
- Bus Enumeration
- Address Space and Transaction Routing
- Clarification of Memory space
- System memory vs MMIO
- Prefetchable vs Non-prefetchable
- IO space
- Setting up the BARs as well as the Base and Limit registers
- Switch Routing Mechanism
Topics Below Are Covered In Class
- TLP Format Details
- Normal TLP fields
- TLP Prefixes
- 10-bit Tags
- PCI-SIG Vendor-Defined Messages
- Flow Control
- Flow Control Protocol
- Scaled Flow Control
- Link Feature Exchange
- Flow Control Initialization
- Runtime Flow Control Update Mechanism
- Transaction Ordering
- Simplified Ordering Table overview
- Relaxed and ID-Based Ordering overview
- DLLP Format Details
- DLLPs
- NOP & Data Link Feature DLLPs
- ACK / NAK Protocol
- TLP Error Recovery Mechanism
- Simplified Replay Timer
- Examples of Numerous Error Scenarios
- Nullified Packets and Cut-Through Mode Switches
- Physical Layer Logic (2.5GT/s and 5.0GT/s)
- Block Diagram
- Ordered Sets
- Byte Striping/Unstriping
- Scrambling/Unscambling
- 8b/10b Encoding/Decoding
- Serializing/Deserializing
- Physical Layer Logic (8.0GT/s, 16.0GT/s and 32.0GT/s)
- 128b/130b Encoding/Decoding
- Control SKPs
- Ordered-Set Blocks and Data Blocks
- Data Streams and Packet Framing
- Precoding
- Physical Layer Electrical (all speeds)
- Differential Tx / Rx
- 2.5GT/s and 5.0GT/s De-emphasis
- 8.0GT/s, 16.0GT/s and 32.0GT/s Equalization Concept
- Rx Equalization overview
- Spread Spectrum Clocking (SSC) overview
- Separate Refclk Independent SSC (SRIS) overview
- Link Initialization and Training (LTSSM)
- Detect, Polling, Configuration, L0 States
- Recovery: Link Speed Change
- Recovery: Equalization Process
- 16.0 GT/s Equalization and Config Structures
- Negotiation for skipping parts or all of Tx Equalization
- 32.0 GT/s Equalization and Config Structures
- Error Detection and Handling
- Correctable, Non-Fatal and Fatal Errors
- Advisory Non-Fatal Errors
- Advanced Error Reporting (AER)
- System Resets
- Conventional Reset Mechanisms: Cold, Warm and Hot Reset
- Function Level Reset (FLR)
- 1b/1b Physical Layer (PCIe 6.0)
- PAM4
- Precoding, Gray Coding and Forward Error Correction (FEC)
- LTSSM Updates (TS0s, Tx EQ changes, entering Flit Mode, etc.)
- Flit Mode
- Flit Format
- Error Correction and Flit Retry (Standard vs Selective)
- DLP Bytes in Flit and Flit Types
- Flow Control (Dedicated vs Shared)
- TLP Structure (Header Base, OHC, TLP Trailer, etc.)
- Segments
- L0p
Training Materials
- PDF of course slides
- "PCI Express Technology" eBook (covers up to PCIe 3.0)
- PCI Express 5.0 eLearning course
Prerequisites
A good understanding of basic computer architecture and serial bus architecture. It will help to have some exposure to PCI Express but not a requirement.