High Bandwidth Memory (Up to HBM4E) - 8-Half-Day Course
High Bandwidth Memory (Up to HBM4E) - 8-Half-Day Course

Location: Virtual Classroom

Instructor: John Swindle

Duration: 8 half-days

Date: 02/16/27 to 02/19/27

and: 02/22/27 to 02/25/27

Time: 1pm - 4:30pm US Pacific Time Daily

$2995.00

Price per Learner (volume discounts available for 5 or more learners; contact us for more details)

Overview

High Bandwidth Memory (HBM) is a form of DRAM used on the most capable HPC and SoC platforms. HBM is an evolution of WideIO and WideIO2 with some concepts borrowed from Graphics DRAM. HBM provides the maximum possible bandwidth of any DRAM technology, largely by implementing several very wide channels. All DRAM (PC DRAM, LP DRAM, Graphics DRAM, HBM) are very similar to one another, but there are significant differences in HBM that this course covers in detail. Our course describes HBM architecture up to HBM4E.

Course Outline

DRAM Fundamentals - Half-Day 1-2

  • System Architecture and Intro to DRAM
  • DRAM Device Architecture
  • Packaging and HBM
  • DRAM Controller Basics and Addresses
  • DDR4 Device and Pin Descriptions
  • Signal Routing
  • DDR4 - Bank State Machines, Commands and Waveforms
  • Refresh

 

HBM Topics - Half-Day 3-8

  • System Architecture and Packaging
    • Example Platforms
  • Channel Architecture, Device Organization and Device Architecture
    • Features and Architectures of Previous Technologies (PC and LP DRAMs)
    • HBM Channels and Pseudo channels
  • Signal Descriptions
    • Channel Signals
    • Global Signals
  • Bank State Machines, Commands and Waveforms
    • Simultaneous Row and Column Commands
    • Use of WDQS and RDQS
  • Refresh
    • Auto Refresh
    • Self Refresh
    • Single-bank (Per-bank) Refresh
    • Row Hammer, Target Row Refresh and Refresh Management
  • Electrical Specifications
    • Why so many traditional SI tools (ODT, ZQ cal, etc.) are not present
    • IDD Specification
  • Power Management
    • Power Down
    • Clock Throttling
  • Initialization, Calibration, and Training
    • JEDEC Initialization
      • Mode Registers
      • Initialization Steps
    • Calibration and Training
      • Vref Training
      • Loopback LFSR MISR Training
        • Command Bus (AWORD) Training
        • Data Group (DWORD) Training
      • Duty Cycle Adjustment (DCA) and Duty Cycle Monitoring (DCM)
      • WDQS Interval Oscillator
  • Errors and Error Handling
    • Temperature
    • Address Parity
    • Data Parity
    • Channel Remapping
    • Sideband ECC
    • On-Die ECC
    • Post Package Repair
      • Self-Repair
      • Hard and Soft Repair
  • Overview of IEEE 1500

Training Materials

  • PDF of course slides
  • HBM4E Architecture eLearning

Prerequisites

 Digital design and computer architecture background.