UCIe - Universal Chiplet Interconnect Express

Universal Chiplet Interconnect Express (UCIe) is an open industry standard, multi-protocol, high-bandwidth (up to 32GT/s per lane), die-to-die (chiplet), interconnect that standardizes inter-die communication on-package. The UCIe 1.1 specification enables users to mix and match chiplet components from a multi-vendor ecosystem for System-on-Chip (SoC) build. The UCIe spec describes a standardized port and interconnect with physical layer, protocol stack and software model that enables inter-chiplet communication. UCIe supports multiple protocols such as PCIe, CXL, and a raw mode that can be used to map any protocol of choice (assuming both ends support it) on top of a common Physical and Link layer. The spec describes elements needed for SoC design such as the application layer, form-factors relevant to the package including bump location, power delivery and thermal solution.

The initial protocols being mapped to UCIe are PCIe and CXL and are done using a Flit packet format for communication. Both PCIe and CXL protocol mappings will enable more on-package integration by replacing the PCIe SERDES PHY, the PCIe/CXL Logical Physical layer and the Link Level Retry (LLR) state-machines with a UCIe Adapter and PHY in order to improve the power and performance characteristics. UCIe also supports a protocol-agnostic raw mode to enable other protocols to be mapped.

MindShare’s comprehensive UCIe Architecture course provides a solid foundation to understanding die-to-die architecture and use of UCIe retimers to extend connectivity beyond the package. The course describes port architecture details including protocol layer, die-to-die adapter layer, logical physical layer and electrical physical layer. We describe single and multi-module configurations. In addition, the course describes the sideband architecture details. Sideband interface is used for back-channel Link training, access to registers, Link management packets and parameter exchanges with remote Link partner. UCIe register architecture and the mechanism by which UCIe-aware SW discovers UCIe capability is described. An optional section describes a Raw Die-to-Die Interface (RDI) and Flit-aware Die-to-Die Interface (FDI) between the die-to-die adapter layer and physical layer.

All of MindShare's classroom and virtual classroom courses can be customized to fit the needs of your group.

A good working knowledge of PCI Express (PCIe) and Compute Express Link (CXL) is a must. Computer architecture fundamentals. Some knowledge of Intel, AMD or Arm processor architectures.