Modern DRAM (DDR5 / DDR4 / LPDDR5 / LPDDR4) eLearning Course
Let MindShare Bring "DRAM" to Life for You
Modern DRAM (DDR5 / DDR4 / LPDDR5 / LPDDR4) eLearning Course
Instructor(s): John Swindle
Equivalent of: 4-day course
Subscription Length: 120 days
$1595
Course price
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What's Included
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| DRAM eLearning modules (unlimited access for 120 days) |
PDF of Course Slides (yours to keep, does not expire) |
Course Completion Certificate (boost your resume/CV) |
Student Review
"I enjoyed most the instructor's clear background knowledge on the topic, and the clearly explained pictures that the JEDEC standards are missing. Very recommendable course. As mainly HW engineer, focusing on DRAM SI simulation aspects, I was looking for a good base knowledge on the DRAM device operations and protocols in order to understand signaling pin interface. Reading the JEDEC standards is useful, but quickly became boring and very confusing, something the instructor of this course reminds you of multiple occasions during the class. This e-learning course definitely filled the gap, well done. I already had some experience with older LPDDR technology implementation jobs, just following design guides from vendors."
- Raf P.
You Will Learn
- Where JEDEC expects DRAM to appear in a system
- How a DRAM cell is addressed by the controller
- Difference between Banks, Bank Groups and Ranks
- Why the DRAM controller is so complicated
- Activation, Precharge and Refresh
- DDR4 pin definitions
- DDR4 bank state diagram
- DDR4 timing waveforms
- Prefetch Width
- Types of DIMMs
- Fly-By Routing
- PC and LP DRAM device architectures and features including DDR5 and LPDDR5
- DDR5/LPDDR4/LPDDR5 pin definitions
- DDR5/LPDDR4/LPDDR5 bank state diagrams
- DDR5/LPDDR4/LPDDR5 timing waveforms
- DDR5 DIMM PMIC
- Intro to NVDIMM
- Newer forms of Refresh
- POD and LVSTL signaling
- Clock throttling and dynamic voltage changes
- On-Die Termination (ODT)
- JEDEC Initialization and Mode Registers
- Calibration and training, including
- Vref training
- Read and Write calibration
- Write Leveling
- Sources of errors and JEDEC features for handling errors
- Test philosophy and JEDEC features to assist with testing
Course Description
This course is hardware-centric and also describes initialization and training of DRAM devices and controllers. It is suitable for hardware engineers and software/firmware engineers will also benefit. The course is ideal for DRAM controller designers, chipset designers, system board-level design and validation engineers. This course introduces current DRAM technologies, concentrating on DDR4 as a baseline to teach concepts that are common to all DRAMs. The course then continues to cover in detail all new features of DDR5, DDR4, LPDDR5, and LPDDR4.
Course Content
41min to complete
33min to complete
Recommended Prerequisites
None
Benefits of eLearning
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